Semiconductor substrates comprising two silicon wafers directly bonded to define a silicon/silicon bond interface have many uses, for example, integrated circuits may be fabricated in such substrates, and such integrated circuits may include CMOS and/or bipolar devices, PIN diodes, insulated gate bipolar transistors, and the like. Additionally, micro-mechanical components, such as micro-mirrors, as well as micro-electromechanical components may also be formed in such substrates. Indeed, integrated circuits and micro-mechanical and micro-electromechanical components may be fabricated on the same substrate of such semiconductor substrates. A semiconductor substrate formed from wafers of single crystal silicon and of respective different electrical characteristics is particularly suitable for use in the fabrication of integrated circuits comprising semiconductor devices, such as bipolar devices, PIN diodes and insulated gate bipolar transistors.
In the manufacture of semiconductor bipolar devices, for example, PIN diodes and insulated gate bipolar transistors two silicon layers of different resistivity are required. Typically, the layers are formed by deposited silicon (epitaxy) which are deposited on a substrate. The layers must be relatively thick epitaxial silicon layers and are thus relatively expensive to produce, and may suffer from inherent defects. Additionally, the deposition of epitaxial layers requires thermal cycles for the deposition, and it has been found that such thermal cycles can result in the formation of oxide layers, which reduce the operating efficiency of semiconductor bipolar devices subsequently formed. Single crystal silicon wafers together, on the other hand, suffer from relatively few defects, and by forming a substrate by bonding two single crystal silicon wafers, the respective silicon wafers can be selected to have the desired electrical characteristics for PIN diodes and/or insulated gate bipolar transistors.
However, two problems arise in the preparation of a semiconductor substrate from two directly bonded silicon wafers. Firstly, it is virtually impossible to prevent the formation of an interfacial oxide layer at the bond interface. In practice, respective oxide layers form on the faces of the wafers to be bonded together prior to bonding no matter how much care is taken between preparation of the wafers by polishing and cleaning, and the subsequent bonding of the wafers. During bonding the respective oxide layers may remain as a single oxide layer at the bond interface, or the oxide in the layer may migrate to form oxide islands at the bond interface. Such an oxide layer or oxide islands at the bond interface causes many problems. For example, the oxide, be it an interfacial layer or islands, acts as a barrier to dopant movement across the bond interface, the oxide also acts as a barrier to electron flow, and additionally the presence of oxide increases capacitance at the bond interface. The presence of interfacial oxide also increases the gain of polysilicon emitter components of bipolar devices formed adjacent the interfacial oxide layer or islands. Additionally, the presence of an interfacial oxide layer or interfacial oxide islands at a bond interface of such a semiconductor substrate formed from two wafers may render the semiconductor substrate virtually unusable in connection with micro-mechanical or micro-electromechanical components. In general, the presence of interfacial oxide along the bond interface of such a semiconductor substrate can lead to subsequent deformation and/or fracturing or other such failure of the micro-mechanical or micro-electromechanical component in the semiconductor substrate.
Secondly, in practice it has been found virtually impossible to directly bond a pair of silicon wafers together without interfacial stresses being induced in the silicon/silicon bond interface between the bonded wafers forming the semiconductor substrate. In order to minimise interfacial stresses at the bond interface between a pair of directly bonded wafers, it is recommended in the prior art that the silicon wafers forming the semiconductor substrate should be selected to be of the same crystal plane orientation, and furthermore, that the wafers be aligned so that the facial atoms at the bond faces of the silicon/silicon bond interface are accurately aligned with each other. It is known that once both wafers are of the same crystal plane orientation, and the wafers are aligned with each other so that the facial atoms at the bond faces of the respective wafers are accurately aligned at the bond interface, virtually no interfacial stress will develop at the bond interface of the respective wafers.
However, in practice it has been found virtually impossible to accurately align the wafers so that the facial atoms at the bond faces of the respective wafers are accurately aligned at the bond interface. Typically, the wafers are circular, and are provided with a straight alignment edge for facilitating alignment of one wafer with the other. Thus, alignment of the wafers is effectively a mechanical or optical operation whereby the respective alignment edges of the wafers are aligned with each other. Mechanical and optical alignment systems do not permit alignment of the wafers with the degree of accuracy required in order to align the wafers with their respective facial atoms aligned with each other. Thus, in general, the facial atoms at the silicon/silicon bond interface of such bonded wafers are seldom if ever accurately aligned, and if accurately aligned, in general, are aligned by accident only. It has been found that when misaligned, stresses build up between the facial atoms at the bond interface, thus leading to interfacial stresses at the bond interface. Such stresses have a number of disadvantages. For example, electrical resistance at the silicon/silicon bond interface increases with interfacial stress, and furthermore, interfacial stresses can lead to bowing and even fracturing of micro-mechanical components, for example, micro-mirrors, where such components are fabricated in the semiconductor substrate formed by such bonded wafers. Additionally, interfacial stresses induced in the bond interface between directly bonded wafers of such semiconductor substrates cause crystal dislocations in the silicon at and near the bond interface. Such crystal dislocations can act as trapping and recombination sites of charge carriers, and can also accumulate chemical impurity species. Both of these effects degrade the performance of electronic devices formed in such semiconductor substrates.
There is therefore a need for a method for bonding two silicon wafers together in which interfacial stresses and interfacial oxide along the bond interface of the wafers are minimised. There is also a need for a semiconductor substrate formed from two directly bonded silicon wafers in which interfacial stresses and interfacial oxide along the bond interface of the respective wafers are minimised. In particular, there is a need for such a semiconductor substrate which is suitable for subsequent use in the fabrication of electronic devices, such as, for example, CMOS devices, bipolar devices, PIN diodes, insulated gate bipolar transistors and other such devices, as well as micro-mechanical and micro-electromechanical components. Furthermore, there is a need for a semiconductor on insulator structure which is suitable for subsequent use in the fabrication of electronic devices, such as, for example, CMOS devices, bipolar devices, PIN diodes, insulated gate bipolar transistors, as well as micro-mechanical and micro-electromechanical components.
The present invention is directed towards providing a method for direct bonding two silicon wafers together for minimising interfacial oxide and/or minimising interfacial stresses along the silicon/silicon bond interface. The invention is also directed towards providing a semiconductor substrate comprising two silicon wafers directly bonded together in which interfacial oxide and/or interfacial stresses along the silicon/silicon bond interface are minimised. Further, the invention is directed towards providing a semiconductor on insulator structure, and a method for preparing such a semiconductor on insulator structure.